1. Field of the Invention
This invention relates generally to computer systems, and more particularly to methods for determining maximum communication rate between devices interconnected via I/O buses in a computer system.
2. Description of the Related Art
Modern computer systems often utilize one or more buses to connect to peripheral devices to enhance its resources. For example, the resources of a computer system may be substantially increased by attaching one or more peripheral devices such as disk drives, tape drives, printers, scanners, optical drives, and the like. Generally, the peripheral devices are attached to the computer system by means of a bus (e.g., cable).
One of the most popular buses is the well known small computer systems interface (SCSI) bus, which is defined in conformity with SCSI protocols (e.g., SCSI-1, SCSI-2, SCSI-3, etc.), which are incorporated herein by reference. The SCSI protocols are designed to provide an efficient peer-to-peer I/O interface between a host computer system and its peripheral devices. The SCSI interfaces may be operated over a wide range of media and transfer rates. For example, Table 1 illustrates representative parameters for data throughput of exemplary SCSI interfaces.
As shown in Table 1, the data throughputs of the SCSI buses vary as the number of data bits transferred, the bus speed, and the type of signal are changed. For example, the maximum data throughput (e.g., data transfer rate) of Ultran SCSI bus is four times that of SCSI-2 bus. This is because the number of data bits transferred and the bus speed of the former bus is twice that of the latter.
The signal type also affects the transfer rate as shown in Table 1. Recently, the Ultra2 SCSI specification has been adopted in the industry to provide greater data transfer rate and cable length. It defines a new Low Voltage Differential (LVD) I/O interface, which uses a pair of wires to carry a signal. This allows for faster data rate of 80 MB/sec and a longer cable (up to 12 or 25 meters depending on load) with less susceptibility to noise than traditional single-ended (SE) signaling.
As is well known in the art, an SCSI bus is generally implemented as a cable having a set of wires. For example, the SCSI-1 cable has 50 wires. Of these 50 wires, 8 wires are for data, 1 wire is for parity, 9 wires are for control, 25 wires are for ground, and the remaining wires are for power or are reserved for future use. The 8 data wires are used to carry 8 bits of data in parallel.
In general, an SCSI bus may accommodate a plurality of SCSI devices up to a number equal to the number of data bits in the SCSI bus. For example, the SCSI-2 bus may accommodate up to eight devices, of which one is usually an SCSI host adapter. The SCSI host adapter functions to convert or otherwise translate signals between the host computer and the peripheral devices.
FIG. 1A illustrates a block diagram of an exemplary computer system 100 having a host computer 102, an SCSI host adapter 104, a plurality of SCSI devices 106, and an SCSI bus 108. The host computer 102 is coupled to the SCSI host adapter 104 by means of a host bus 110 such as PCI bus or the like. The host adapter 104 is also coupled to the SCSI devices 106 by means of the SCSI bus 108. Under the current SCSI specifications, the SCSI bus 108 may interconnect up to 7 or 15 target SCSI devices 106 to the host adapter 104 depending on the type of SCSI bus implemented. The target SCSI devices 106 may be devices such as disk drives, tape drives, printers, scanners, optical drives, or any other devices that meet the SCSI specification.
In this arrangement, the host adapter 104 controls communication between the host computer 102 and the SCSI devices 106. Specifically, the host adapter 104 is configured to receive data, address, and control signals from the host computer 102 via the host bus 110 and convert the signals into corresponding SCSI compatible data, address, and control signals. Similarly, the host adapter 104 is also configured to receive SCSI compatible data, address, and control signals from the SCSI devices 106 through the SCSI bus 108 and convert them into corresponding host-bus compatible data, addressing, and control signals.
FIG. 1B is a more detailed block diagram of the host adapter 104 having an SCSI host adapter chip 112, an SCSI bus interface 114, a host interface 116, and a ROM 118. The host interface 116 is configured to provide a physical connection to the host bus 110. The SCSI host adapter chip 112 is configured to interface with the host and SCSI bus interfaces 116 and 114. The SCSI host adapter chip 112 is well known in the art and may be implemented, for example, by using ACI-7890A packaged semiconductor device, which is available from Adaptec Inc., of Milpitas, Calif.
The SCSI host adapter chip 112 uses the ROM 118 to store operating instructions that can be read into the memory of the host computer system 102 and executed by a host processor to communicate with the host adapter 104. The operating instructions stored within the ROM 118 typically include either a BIOS image or some other type of host-bus compatible platform operating system driver.
Currently, when the computer system 100 powers up, the SCSI host adapter 104, as initiator, interrogates the SCSI bus 108 to determine which devices are connected to the bus 108. This scan of the bus is done by the operating system module (OSM) part of the BIOS code. The interrogation consists of the initiator arbitrating for the bus, winning the arbitration, and selecting each device ID to check for a response from an associated SCSI device. If a particular ID responds, the initiator sends an INQUIRY command and the device responds with data identifying the device such as manufacturer, serial number, etc.
At boot-up, the host adapter 104 accesses the ROM 118 and attempts to recognize devices connected to the SCSI bus 108. In addition, it performs initial testing on speed and width of the SCSI bus 108 and starts boot process. However, users often connect the SCSI devices and cable in violation of SCSI specification. For example, the BIOS in the ROM 118 may be set to a speed higher than what the computer system 100 is capable of handling. As a result, the boot process fails and an error condition is generated. In response, the user manually resets the parameters to a different bus speed and/or width in the BIOS of the host adapter and reboots the computer system 100.
Unfortunately, this trial and error process imposes a substantial burden for many users in terms of time and labor needed to manually set the parameters for proper boot-up and operation. In addition, the speed thus set is often lower than what the system is capable of operating reliably. For example, users often set the parameters of host adapters to operate at a lowest possible speed (e.g., 5 MB/sec) to provide the least probability of failure. This means that the computer system may operate at less than its full capacity. Hence, the resources of the computer system are not efficiently utilized.
In view of the foregoing, there is a need for a method and system for setting data throughput parameters to provide the highest data throughput between a host adapter and a target device over a bus without requiring users to manually adjust and set bus parameters.
The present invention fills these needs by providing method and system for automatically determining maximum data throughput rate over a bus. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium. Several inventive embodiments of the present invention are described below.
In one embodiment, the present invention provides a method of determining maximum data throughput between a host adapter and one or more target devices coupled to the host adapter through a bus. In this method, a first set of device identifying data is obtained from a target device over the bus at a minimum data throughput rate. Then, a maximum data throughput rate is negotiated between the host adapter and the target device over the bus. Next, a second set of device identifying data is obtained from the target device over the bus at the negotiated maximum data throughput rate. When the first and second sets of device identifying data are identical, the host adapter and the target device are operated over the bus at the negotiated maximum data throughput rate.
In another embodiment, a method of setting parameters to provide maximum data throughput over a bus is disclosed. The bus is coupled between a host adapter and one or more target devices. In this embodiment, a target device is selected among the one or more target devices. Then, one or more parameters are set to specify a maximum data throughput rate. The parameters include data width, bus speed, or signal type. A write and read test is then performed at the maximum data throughput rate over the bus. Specifically, the write and read test transfers a test data pattern between the host adapter and the selected target device where the test data pattern is configured for testing signal transmission characteristics of the bus at the maximum data throughput. The write and read test determines whether the bus is capable of reliably operating at the maximum data throughput rate.
In yet another embodiment, the present invention provides a system for determining maximum data transfer speed over a bus coupled between target devices. The system includes a bus for transmitting data, a host computer, one or more target devices coupled to the bus, and a host adapter. The host computer includes a host processor and a RAM and is configured to generate one or more test patterns for testing the bus. The host adapter is coupled between the host computer and the bus for interfacing the target devices with the host computer. The host adapter is configured to set parameters to specify a maximum data transfer speed for the bus. In addition, the host adapter is further configured to select a test pattern and transmit a first copy of the test pattern to a selected target device. The selected target device is configured to transmit a second copy of the first copy to the host adapter. When the second copy is identical to the test pattern, the bus is determined to be capable of operating at the maximum data transfer rate.
By automatically determining and setting the maximum data throughput rate, the users are thus relieved from the tedious task of manually setting parameters and rebooting until the computer system boots up properly. This also means that the host adapter and target devices are ensured of operating reliably at the highest data transfer speed possible. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.